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1 features ? third generation programmable logic structure C easily achieves gate utilization factors of 80 percent ? increased logic flexibility C 86 inputs and 72 sum terms ? flexible output macrocell C 48 flip-flops - 2 per macrocell C 3 sum terms - can be or'ed and shared ? high-speed ? low-power less than 0.5 ma typical (ATV2500L) ? multiple feedback paths provide for buried state machines and i/o bus compatibility ? asynchronous clocks and resets C multiple synchronous presets - one per four or eight flip-flops ? proven and reliable high speed cmos eprom process C 2000v esd protection C 200 ma latchup immunity ? reprogrammable - tested 100% for programmability ? 40-pin dual-in-line and 44-lead surface mount packages block diagram description the atv2500h/l is the most powerful programmable logic device available in a 40- pin package. increased product terms, sum terms, and flip-flops translate into many more usable gates. high gate utilization is easily obtainable. the atv2500h/l is organized around a global bus. all pin and feedback terms are always available to every logic cell. each of the 38 logic pins and their complements are array inputs, as well as the true and false outputs of each of the 48 flip-flops. high-density uv-erasable programmable logic device atv2500h ATV2500L rev. 0025eC05/98 (continued) pin configurations pin name function in logic inputs i/o bidirectional buffers i/o, 0,2,4.. even i/o buffers i/o, 1,3,5.. odd i/o buffers * no internal connection vcc +5v supply dip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 in in in i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 vcc i/o17 i/o16 i/o15 i/o14 i/o13 i/o12 in in in in in in in in i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 gnd i/o23 i/o22 i/o21 i/o20 i/o19 i/o18 in in in plcc/lcc * = no connect 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 i/o2 i/o3 i/o4 i/o5 vcc vcc i/o17 i/o16 i/o15 i/o14 i/o13 i/o7 i/o8 i/o9 i/o10 i/o11 gnd gnd i/o23 i/o22 i/o21 i/o20 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o12 in in in in in in in * i/o18 i/o19 i/o1 i/o0 * in in in in in in in i/o06
atv2500h/l 2 there are 416 product terms available. four product terms are input to each sum term. the three sum terms per logic cell can be combined to provide up to twelve product terms, combinatorial and registered. independent of output config- uration, the two flip-flops are always usable, and always have at least four product term inputs. product terms are available providing asynchronous resets, flip-flop clocks, and output enables. one reset and one clock term are provided per flip-flop, with one enable term per output. eight product terms provide local synchro- nous presets, divided up into banks of four and eight flip- flops. register preload and buried register observability simplify testing. the device has an internal power up clear function. functional logic diagram atv2500h/l
atv2500h/l 3 functional logic diagram description the atv2500h/l functional logic diagram describes the interconnections between the input, feedback pins and logic cells. all interconnections are routed through the glo- bal bus. the atv2500h/l is a straightforward and uniform pld. the twenty-four macrocells are numbered 0 through 23. each macrocell contains 17 and gates. all and gates have 172 inputs. the five lower product terms provide ar1, ck1, ck2, ar2, and oe. these are: one asynchronous reset and clock per flip-flop, and an output enable. the top twelve product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. eight synchronous preset terms are distributed in a 2/4 pat- tern. the first four macrocells share preset 0, the next two share preset 1, and so on, ending with the last two macro- cells sharing preset 7. the fourteen dedicated inputs and their complements use the numbered positions in the global bus as shown. each macrocell provides six inputs to the global bus: (left to right) flip-flop q2 true and false, flip-flop q1 true and false, and the pin true and false. the positions occupied by these sig- nals in the global bus are the six numbers in the bus dia- gram next to each macrocell. absolute maximum ratings* temperature under bias............................... -55c to + 125c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. max- imum output pin voltage is vcc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature .................................... -65c to + 150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) integrated uv erase dose.............................. 7258 w.sec/cm 2
atv2500h/l 4 output logic, registered output logic, combinatorial these diagrams show equivalent logic functions, not necessarily the actual circuit implementation. note: 1. these 4 terms are shared with d1. note: 1. these 4 terms are shared with d1. s2 s1 s0 terms in output configuration d1 d2 0 0 0 8 4 registered (q1) 010124 (1) registered (q1) s3 output configuration 0 active low 1 active high s2 s1 s0 terms in output configuration d1 d2 1004 (1) 4 combinatorial (8 terms) 1 0 1 4 4 combinatorial (4 terms) 1104 (1) 4 (1) combinatorial (12 terms) s3 output configuration 0 active low 1 active high dc and ac operating atv2500h-25 atv2500h/l-30 atv2500h/l-35 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c-40 c - 85 c-40 c - 85 c mil. -55 c - 125 c-55 c - 125 c-55 c - 125 c vcc power supply 5v 10% 5v 10% 5v 10%
atv2500h/l 5 note: 1. not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. this para me- ter is only sampled and is not 100% tested. see absolute maximum ratings. note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. dc characteristics symbol parameter condition min typ max units i li input load current v in = -0.1v to v cc + 1v 10 m a i lo output leakage current v out = -0.1v to v cc + 0.1v 10 m a i cc power supply current v cc = max, v in = gnd or v cc outputs open ATV2500L com. 0.5 5 ma ind.,mil. 0.5 10 ma atv2500h com. 80 160 ma ind.,mil. 80 180 ma i os (1) output short circuit current v out = 0.5v -120 ma v il input low voltage -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il, i ol = 8 ma com,ind; 6 ma mil. 0.5 v v oh output high voltage i oh = -100 m av cc - 0.3 v i oh = -4.0 ma 2.4 v pin capacitance (f = mhz, t = 25 c) (1) typ max units conditions c in 46 pf v in = ov c out 812pf v out = ov
atv2500h/l 6 ac waveforms (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0.0v and 3.0v, unless otherwise specified. note: 1. buried registers include all 24 q2 registers and any of the 24 q1 registers in macrocells configured as combinatorial. ac characteristics for the ATV2500L symbol parameter ATV2500L-30 ATV2500L-35 units min max min max t pd input or feedback to non-registered output 30 35 ns t ea input to output enable 30 35 ns t er input to output disable 30 35 ns t co clock to output 5 30 5 35 ns t cf clock to feedback 10 20 15 20 ns t si1 input setup time, output register 20 22 ns t si2 input setup time, buried register (1) 20 22 ns t sf feedback setup time 10 15 ns t h1 hold time, output register 10 15 ns t h2 hold time, buried register (1) 55ns t w clock width 15 17 ns t p clock period 30 35 ns f max maximum frequency (1/t p )3328mhz t aw asynchronous reset width 18 20 ns t ar asynchronous reset recovery time 18 20 ns t ap asynchronous reset to registered output reset 30 35 ns
atv2500h/l 7 note: 1. buried registers include all 24 q2 registers and any of the 24 q1 registers in macrocells configured as combinatorial. input test waveforms and measurement levels t r , t f < 5 ns (10% to 90%) output test loads ac characteristics for the atv2500h symbol parameter atv2500h-25 atv2500h-30 atv2500h-35 units minmaxminmaxminmax t pd input or feedback to non-registered output 25 30 35 ns t ea input to output enable 25 30 35 ns t er input to output disable 25 30 35 ns t co clock to output 10 25 12 30 15 35 ns t cf clock to feedback 10 18 12 20 15 20 ns t si1 input setup time, output register 10 12 15 ns t si2 input setup time, buried register (1) 555ns t sf feedback setup time 7 10 15 ns t h1 hold time 5 5 5 ns t w clock width 10 12 15 ns t p clock period 25 30 35 ns f max maximum frequency (1/t p )403328mhz t aw asynchronous reset width 15 18 20 ns t ar asynchronous reset recovery time 15 18 20 ns t ap asynchronous reset to registered output reset 25 30 35 ns
atv2500h/l 8 preload and observability of registered outputs the atv2500h/l's registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. this feature will simplify testing since any state can be forced into the registers to control test sequencing. a v ih level on the odd i/o pins will force the appropriate register high; a v il will force it low, independent of the polarity or other configuration bit settings. the preload state is entered by placing an 11v to 14v sig- nal on pin 38 on the dip and pin 42 on the smp. when the clock term is pulsed high, (pin 21 on the dip, pin 23 on the smp) the data on the i/o pins is placed into the 12 regis- ters chosen by the q select and even/odd select pins. register 2 observability mode is entered by placing an 11v to 14v signal on pin 2 (dip or smp). in this mode, the con- tents of the buried register bank will appear on the associ- ated outputs when the oe control signals are active. power-up reset the registers in the atv2500h/l are designed to reset dur- ing power-up. at a point delayed slightly from v cc crossing 3.8v, all registers will be reset to the low state. the output state will depend on the polarity of the output buffer. this feature is critical for state machine initialization. how- ever, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the fol- lowing conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock term high, 3. the signals from which the clock is derived must remain stable during t pr . level forced on odd i/o pin during preload cycle. q select pin state even/ odd select even q1 state after cycle even q2 state after cycle odd q1 state after cycle odd q2 state after cycle v ih low low high x x x v il low low low x x x v ih high low x high x x v il high low x low x x v ih low high x x high x v il low high x x low x v ih high high x x x high v il high high x x x low parameter description min typ max units t pr power-up reset time 600 1000 ns
atv2500h/l 9 security fuse usage a single fuse is provided to prevent unauthorized copying of the atv2500h/l fuse patterns. once programmed, the outputs will read programmed during verify. the security fuse should be programmed last, as its effect is immediate. the security fuse also inhibits preload and q2 observabil- ity. atmel cmos plds atmel's erasable programmable logic devices utilize an advanced 1.25-micron cmos eprom technology. this technology's state of the art features are the optimum com- bination for plds: ? cmos technology provides high speed, low power, and high noise immunity. ? eprom technology is the most cost effective method for producing plds - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. ? eprom reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible plds. ? atmel's eprom process has proven extremely reliable in the volume production of a full line of advanced eprom memory products, from 64k to one-megabit devices. using the atv2500h/l's many advanced features the atv2500h/l's flexibility puts more usable gates in 40 pins than other plds. some of the atv2500h/l's key fea- tures are: ? asynchronous clocks - each of the flip-flops in the atv2500h/l has a dedicated product term driving the clock. the user is no longer con- strained to using one clock for all the registers. buried state machines, counters, and registers can all coexist in one device, while running on separate clocks. the atv2500h/l clock period matches that of similar synchronous devices. ? a total of 48 registers - the atv2500h/l provides two flip-flops for each output macrocell - a total of 48. each register has its own clock and reset product terms, as well as its own sum term. ? independent i/o pin and feedback paths - each i/o pin on the atv2500/h has a dedicated input path. each of the 48 registers has individual feedback terms into the array. this feature, combined with individual product terms for each i/o's output enable, facilitates designs using bi-directional i/o buses. ? three sum terms per macrocell - the atv2500h/l macrocell can be configured with one sum term feeding the output, and still have two sum terms feeding the flip-flops. this is the simplest method for inter- facing with an i/o bus, and no flip-flops need be sacrificed. ? combinable sum terms - each output macrocell's three sum terms can be combined in an or gate before the output or the register. this pro- vides up to twelve product terms per output or flip-flop. when the registered output configuration is chosen, eight terms are automatically available to d1. the four terms feeding d2 can also be shared with d1, giving it a total of twelve. in the combinatorial mode, four, eight, or twelve terms can feed the output, with the middle four still driving d1 and the bottom four still driving d2. programming software support software which is capable of transforming boolean equa- tions, state machine descriptions and truth tables into jedec files for the atv2500h/l is currently available from several pld software vendors. please refer to the pro- grammable logic development tools section for a com- plete listing of the pld software support. erasure characteristics the entire memory array of an atv2500h/l is erased after exposure to ultraviolet light at a wavelength of 2537 ?. complete erasure is assured after a minimum of twenty minutes exposure using 12,000 m w/cm 2 intensity lamps spaced one inch away from the chip. minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of fifteen w ? sec/cm 2 . to prevent unintentional erasure, an opaque label is rec- ommended to cover the clear window on any uv erasable pld which will be subjected to continuous fluorescent indoor lighting or sunlight.
atv2500h/l 10 note: all normalized values referenced to maximum specification in ac characteristics section of datasheet.
atv2500h/l 11
atv2500h/l 12 ordering information t pd (ns) t co (ns) f max (mhz) ordering code package operation range 25 25 40 atv2500h-25dc atv2500h-25jc atv2500h-25kc atv2500h-25lc atv2500h-25pc 40dw6 44j 44kw 44lw 40p6 commercial (0 c to 70 c) atv2500h-25di atv2500h-25ji atv2500h-25ki atv2500h-25li atv2500h-25pi 40dw6 44j 44kw 44lw 40p6 industrial (-40 c to 85 c) atv2500h-25dm atv2500h-25km atv2500h-25lm 40dw6 44kw 44lw military (-55 c to 125 c) atv2500h-25dm/883 atv2500h-25km/883 atv2500h-25lm/883 40dw6 44kw 44lw military/883c (-55 c to 125 c) class b, fully compliant 30 30 33 atv2500h-30dc atv2500h-30jc atv2500h-30kc atv2500h-30lc atv2500h-30pc 40dw6 44j 44kw 44lw 40p6 commercial (0 c to 70 c) atv2500h-30di atv2500h-30ji atv2500h-30ki atv2500h-30li atv2500h-30pi 40dw6 44j 44kw 44lw 40p6 industrial (-40 c to 85 c) 35 35 28 atv2500h-35dc atv2500h-35jc atv2500h-35kc atv2500h-35lc atv2500h-35pc 40dw6 44j 44kw 44lw 40p6 commercial (0 c to 70 c) atv2500h-35di atv2500h-35ji atv2500h-35ki atv2500h-35li atv2500h-35pi 40dw6 44j 44kw 44lw 40p6 industrial (-40 c to 85 c) 25 25 40 5962-91545 02m qa 5962-91545 02m xx 5962-91545 02m yx 40dw6 44lw 44kw military/833c (-55 c to 125 c) class b, fully compliant
atv2500h/l 13 30 30 33 ATV2500L-30dc ATV2500L-30jc ATV2500L-30kc ATV2500L-30lc ATV2500L-30pc 40dw6 44j 44kw 44lw 40p6 commercial (0 c to 70 c) ATV2500L-30di ATV2500L-30ji ATV2500L-30ki ATV2500L-30li ATV2500L-30pi 40dw6 44j 44kw 44lw 40p6 industrial (-40 c to 85 c) ATV2500L-30dm ATV2500L-30km ATV2500L-30lm 40dw6 44kw 44lw military (-55 c to 125 c) ATV2500L-30dm/883 ATV2500L-30km/883 ATV2500L-30lm/883 40dw6 44kw 44lw military (-55 c to 125 c) class b, fully compliant 35 35 28 ATV2500L-35dc ATV2500L-35jc ATV2500L-35kc ATV2500L-35lc ATV2500L-35pc 40dw6 44j 44kw 44lw 40p6 commercial (0 c to 70 c) ATV2500L-35di ATV2500L-35ji ATV2500L-35ki ATV2500L-35li ATV2500L-35pi 40dw6 44j 44kw 44lw 40p6 industrial (-40 c to 85 c) 30 30 33 5962-91545 03m qa 5962-91545 03m xx 5962-91545 03m yx 40dw6 44lw 44kw military/833c (-55 c to 125 c) class b, fully compliant ordering information (continued) t pd (ns) t co (ns) f max (mhz) ordering code package operation range package type 40dw6 40-lead, 0.600" wide windowed, ceramic dual in-line package (cerdip) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 44kw 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) 44lw 44-pad, windowed, ceramic leadless chip carrier (lcc) 40p6 40-lead, 0.600" wide plastic dual in-line package otp (pdip)
atv2500h/l 14 packaging information .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq .045(1.14) x 45 .032(.813) .026(.660) .050(1.27) typ .500(12.7) ref sq .035(.889) x 45 .010(.254) .006(.152) .021(.533) .017(.432) .630(16.0) .590(15.0) .045(1.14) .035(.889) .120(3.05) .090(2.29) .180(4.57) .156(3.96) .665(16.9) .645(16.4) .695(17.7) .685(17.4) sq sq .025(.635) radius max (3x) 40dw6, 40-lead, 0.600" wide windowed, ceramic dual in-line package (cerdip) dimensions in inches and (millimeters) mil-std-1835 d-5 config a 44j, 44-lead, plastic j-leaded chip carrier otp (plcc) dimensions in inches and (millimeters) 44kw, 44-lead, windowed, ceramic j-leaded chip carrier (jlcc) dimensions in inches and (millimeters) mil-std-1835 c-j1 44lw, 44-pad, windowed, ceramic leadless chip carrier (lcc) dimensions in inches and (millimeters) mil-std-1835 c-5
atv2500h/l 15 packaging information 2.07(52.6) 2.04(51.8) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.900(48.26) ref 40p6, 40-lead, 0.600" wide plastic dual inline package otp (pdip) dimensions in inches and (millimeters) jedec standard ms-001 ac

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